Sixth International Symposium on Low Temperature Electronics - Summary

View of San Francisco from Marin

The Sixth International Symposium on Low Temperature Electronics (6 September 2001, San Francisco, California) was a one-day Symposium as part of the Joint International Meeting of the Electrochemical Society and the International Society of Electrochemistry. Twelve papers were presented, covering a variety of topics in basic and applied electronic devices and circuits at low temperatures. There are no published proceedings from this Symposium.

The morning session began with a presentation of "Low Temperature Characteristics of Ultra-short Gate Length Ultra-thin SOI MOSFETs and Si Nanowire Devices" by Eiichi Suzuki of the National Institute of Advanced Industrial Science and Technology, Ibaraki, Japan (co-authors T. Tsutsumi, K. Ishii and S. Kanemaru). He described work toward nanodevices based on scaling down of Si MOS/CMOS transistors and incorporating quantum effects. He described the excellent low-temperature behavior of MOS devices with gates as short as 40 nm and made using SOI (silicon-on-insulator). He also described work on Si nanowire transistors for memory that exhibit single-electron behavior at cryogenic temperatures.

The following talk, "Performance and Reliability of Advanced pMOSFET Devices," was presented by Bogdan Cretu of ENSERG, Grenoble, France (co-authors F. Balestra and G. Ghibaudo). He summarized experimental cryogenic-temperature investigations of sub-0.1 μm gate length Si MOSFETs and their enhanced characteristics in the areas of leakage, mobility, transconductance, and subthreshold slope. Also, measurements on hot-carrier effects, which generally become worse as temperature lowers, were made in order to extrapolate and predict device lifetime and determine operating limits.

In the next talk, "The Impact of the Drain Saturation Voltage on the Multiplication Current Modeling of MOSFETs at Liquid Helium Temperatures," Cor Claeys of IMEC, Leuven, Belgium (co-author E. Simoen) discussed the behavior of CMOS devices at liquid-helium temperatures, which is of interest for scientific spacecraft applications. They wish to model the "kink" and hysteresis effects that are detrimental to using CMOS at deep cryogenic temperatures. He described their work in comparing three different extraction techniques for determining the drain saturation voltage, a key parameter for modeling these effects, and concluding that the "output resistance" technique is the most reliable.

In the following talk, "Carrier Freeze-out and Relaxation Effects in CMOS N-channel MOSFETs at Cryogenic Temperatures under Dynamic Operating Conditions," Gerald Oleszek of the Univ. of Colorado, Colorado Springs, Colorado, USA summarized experimental investigations comparing n-channel MOS transistors having tied wells to those with floating wells. The investigations compared hot-carrier effects ("kink" and hysteresis) at cryogenic temperatures for the two MOS transistor configurations and concluded that the effects were reduced for the floating-well transistors.

The final morning talk,"Prospects for the Operation of Deep Sub-0.1μm MOSFETs at Low Temperature" was presented by Francis Balestra of Lab. de Physique des Composants à Semiconducteurs, ENSERG, Grenoble, France (co-author G. Ghibaudo) on short-gate (sub-0.1 μm) MOSFETs. He reviewed the reasons for interest in these devices and their low-temperature behavior including reverse-short-channel, gate-induced drain leakage, and hot-carrier effects. He concluded by showing Coulomb oscillations in 50-nm MOSFETs at 4 K and 0.035 K.

The afternoon session began with a preface by Richard Patterson of NASA Glenn Research Center, Cleveland, Ohio, USA who summarized the reasons for interest in deep-cryogenic (down to ~30 K) electronics for spacecraft and its applications. The following talks by Vik Kapoor and Rufus Ward described work on cryogenic power electronics supported by NASA Glenn.

The first two afternoon talks, "Low Temperature Space-Borne Power Electronics and Semiconductor Devices" and "Compound Semiconductor Devices for Space-Borne Power Electronic Systems," were combined and given by Vik Kapoor of the Univ. of Toledo, Toledo, Ohio, USA (co-authors C. Melkonian, T. Miller, D. Bernardon, J. Dickman and R. Patterson). He first described their comparisons of various Si and GaAs semiconductor devices (bipolar, MOSFET, CMOS, and MESFET devices) for cryogenic power applications. These transistors were evaluated in dc/dc converters and the CMOS converter was found to be the most reliable of those based on the Si transistors; also, the GaAs MESFET converter worked well down to 77 K. He also described their success in operating a 10-W dc/dc converter down to 20 K using InGaAs MISFETs.

The next talk, "Investigation of Ge Transistors for Cryogenic Power Applications," was given by Rufus Ward of GPD Optoelectronics, Salem, New Hampshire, USA (co-authors R. Kirschman, O. Mueller, R. Patterson, J. Dickman and A. Hammoud). He summarized evaluation and development of Ge-based diodes, bipolar transistors, JFETs, and metal-insulator-semiconductor devices for use down to 20 K in power circuits and their projected advantages over Si-based devices.

Randall Kirschman presented the following talk, "Development of Cryogenic Ge JFETs - IV," (co-authors R. Ward, M. Jhabvala, R. Babu, D. Camin, V. Grassi, C. Colombo, K. Kandiah and J. Rosenberg) about progress in developing a transistor for very low noise preamplification at deep cryogenic temperatures (to the liquid-He range). The approach uses JFETs based on germanium. So far, low noise has been achieved down to 30 K and there are plans to extend the low noise capability down to 4 K and below.

This was followed by "Low Frequency Noise versus Temperature Spectroscopy of Si and Ge JFETs," by Valerio Grassi of the Univ. of Milan and INFN, Milan, Italy (co-authors C. Colombo and D. Camin). He described their instrumentation for automatic dc and noise characterization of semiconductor devices over the cryogenic temperature range. By means of this instrumentation and analysis of the measured noise spectral components (Lorentzians) they are able to identify parameters of impurities in the devices.

Yong Jin of CNRS, Bagneux cedex, France (co-author T. Lucas) presented "Experimental Investigation of pHEMT at 4.2 K: Fabrication and Characterization." He reported on the fabrication of pseudomorphic (Al,In)GaAs/GaAs HEMTs and their dc and low-frequency (approximately <105 Hz) noise characteristics at 4.2 K. These HEMTs exhibit low noise voltage that is approximately 1/f, which he compared to the Hooge theory.

The next scheduled talk, "Analysis of BJT/JFET PTAT Sensor Operation," (authors S. Amon, M. Mozek, D. Vrtacnik, D. Resnik and M. Cvar of Univ. of Ljubljana, Ljubljana, Slovenia) was not given.

The final talk of the Symposium, "Transient Phenomena during the Self-Heating of Silicon Devices Operating at Low Temperatures," was presented by Javier De la Hidalga-W of INAOE, Puebla, Mexico (co-author M. Deen). He explained that---depending on the ambient temperature---either electrical or thermal phenomena might dominate the electrical/thermal transients in the active region of a Si device during switching. His analysis indicates that below approximately 50 K electrical rather than thermal time constants can be the determining factor.

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Adapted from "Extreme-Temperature Electronics Newsletter", Issue #3, 5 October 2001

Copyright © 2001-2002 by Randall K. Kirschman.

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